Libdav1d Roadmap: Upcoming AV1 Decoder Optimizations

This article explores the planned future optimizations for libdav1d, the premier open-source AV1 video decoder. As AV1 continues to gain mainstream adoption across streaming platforms, the development team is focusing on key performance enhancements to ensure efficient playback. We detail the upcoming roadmap, including assembly-level optimizations for ARM and x86 architectures, improved multi-threading efficiency, and memory footprint reductions aimed at delivering smooth high-definition playback on both low-power mobile devices and high-end desktop systems.

ARM Architecture and Mobile Enhancements

A primary focus for future libdav1d releases is optimizing performance on ARM-based devices, particularly smartphones, tablets, and single-board computers. The development roadmap includes writing hand-crafted ARM64 NEON assembly for remaining C-fallback functions.

Special attention is being paid to 10-bit and 12-bit depth video decoding, which is essential for High Dynamic Range (HDR) content. By moving more of the pixel-prediction, loop restoration, and film grain synthesis functions from generic C code to highly optimized ARM assembly, mobile devices will experience lower CPU utilization, reduced thermal throttling, and significantly improved battery life during AV1 playback.

x86 AVX2 and AVX-512 Micro-Architectural Tweaks

While libdav1d is already highly performant on x86 platforms, developers continue to squeeze extra performance out of modern PC processors. Future updates will introduce micro-architectural refinements for AMD and Intel CPUs:

• AVX2 Refinements: Rewriting critical hot paths in assembly to reduce instruction cache misses.
• AVX-512 Implementation: Expanding the use of AVX-512 instructions for high-end desktop and server CPUs. This will accelerate heavy decoding workloads, such as 8K resolution playback and high-frame-rate content.

Threading and Scheduling Efficiency

To maximize hardware utilization, libdav1d utilizes a sophisticated frame and tile-threading model. Upcoming releases aim to reduce the synchronization overhead between these threads.

By refining the internal scheduler, the decoder will better balance workloads across asymmetric CPU configurations (such as ARM’s big.LITTLE architecture or Intel’s Performance/Efficient core hybrid layouts). This scheduling optimization prevents “starvation” of faster cores and minimizes latency, ensuring consistent frame delivery without micro-stuttering.

Memory Footprint and Cache Optimization

Reducing memory bandwidth is as critical for performance as raw processing power. Future optimization passes are targeting memory locality to ensure that decoded frame data remains in the CPU’s fast L1/L2/L3 cache as long as possible. By restructuring internal data buffers and minimizing dynamic memory allocations during active decoding streams, libdav1d will achieve a lower overall memory footprint, making it highly viable for extremely constrained embedded systems.